Erasable Programmable Read-only Memories (EPROMs), Electrically Erasable Programmable Read-only Memories (E.sup.2 PROMs), and Flash E.sup.2 PROMs (hereafter collectively, PROMs) have several structures which allow them to hold a charge without refresh for extended periods of time. FIG. 1 shows a top view of a PROM array, FIG. 2 shows a cross section along "AA" of FIG. 1, and FIG. 3 shows a cross section along "BB" of FIG. 1. The charge itself is stored on a "floating gate" 10 also referred to as Poly 1 or P1, which is a structure of polycrystalline silicon (hereafter, poly) surrounded on all sides by a layer of oxide 12. Located superjacent and parallel to this P1 structure is another poly structure, the "control gate" 14 or P2. P1 10 and P2 14 act as the two plates of a capacitor. Below the P1 layer are two N+ junctions, one which acts as the transistor source 16 and the other as the drain 18, which are doped into a P-type substrate 20. The portion of the substrate 20 between the source 16 and the drain 18 is the channel 22. The cell functions like an enhancement-type N-channel metal oxide semiconductor field effect transistor (MOSFET) with two gates of poly.
There are many ways to program a PROM. In one technique, a potential such as 12 V, for example, is applied on the control gate. Simultaneously, a voltage pulse, for example 8 V, is applied between source and drain. The large positive voltage on the control gate establishes an electric field in the insulating oxide. This electric field attracts the electrons generated from the so-called "avalanche breakdown" of the transistor due to the high drain and control gate voltages, and accelerates them toward the floating gate, which they enter through the oxide. In this way the floating gate is charged, and the charge that accumulates on it becomes trapped.
To return the floating gate from a charged state to a state with no charge, the electrons are caused to return to the substrate. In an EPROM, this is accomplished with ultraviolet light which excites the electrons past a certain energy state, thereby allowing them to pass through the oxide and return to the substrate. In an E.sup.2 PROM, this excitation is accomplished with an electrical field.
There are structures that make up a PROM array which are common to several transistors in the array. FIG. 1 is a top view of an array showing the transistor sources 16, drains 18, digit lines 24, floating gates 10, and control or "word" lines 26 which form control gates 14 as they pass over the floating gates 10. Also shown as a dotted line is the "active area" 28 interspersed with areas of field oxide 30. A single word line 26 is common to all transistors in a single column acting as a control gate 14 for all transistors in the column. When the word line is selected it activates all transistors in the column. The source regions 16, which run parallel with the control lines 26, are common to all transistors in two adjacent columns. Individual transistor drains 18 are common to two transistors in adjacent columns. The digit (or bit) lines 24 are common with the drains 18 of all transistors in a single row.
To read the datum stored on a floating gate 10, the control line 26 of the cell to be read is activated, for example by bringing it to between 2.5 V and 3.5 V which causes all transistors in the selected column to become active. This voltage applied to the control gate 26 is above the trip voltage of a cell holding a "1" state, and below the trip voltage of a cell storing a "0". The voltage needed on the transistor channel to trip the transistor, the "threshold voltage" (V.sub.T) is set to a known voltage, for instance 1 V. If a cell is set to a zero, arbitrarily defined by storing -3 V on the floating gate 10, and 3.5 V is applied to the control gate, the net effect on the transistor channel is less than the 1 V needed to trip the transistor. If a cell is set to a one, arbitrarily defined by storing 0 V on the floating gate 10, the net effect on the transistor channel is greater than the 1 V needed to activate the transistor. After the control gate 26 is activated, each cell along that control gate 26 outputs the cell information on their respective digit lines 24, either an OFF if the floating gate is storing a charge or an ON if the cell is not storing a charge. The information on the digit line 24 which corresponds to the cell to be read is obtained with a sense amplifier (not shown), with one sense amp for each digit line.
In a conventional Flash E.sup.2 PROM cell, the floating gate and the control gate are both manufactured from N-type poly. The substrate is P-type conductivity with N.sup.+ junctions which form the source and drain regions. To manufacture N-type poly, a poly structure is doped with atoms having more than four valence electrons (group V or higher), such as arsenic or phosphorus, which introduces negatively charged majority carriers into the silicon and make the semiconductive material somewhat more conductive. To manufacture P-type poly, a poly structure is doped with atoms having less than four valence electrons (group III or lower), such as boron, which introduce positively charged majority carriers and make the semiconductive material somewhat less conductive. The majority charge carrier type is also referred to as conductivity type.
The threshold voltage on a conventional PROM device is set to a desired voltage by performing a "V.sub.T adjust implant" which is a standard enhancement implant. If no V.sub.T adjust implant is performed, the transistor will trip at too low a voltage, for instance 0 V. This would cause the transistor to trip when it should not, thereby indicating that the floating gate is storing a charge when it actually is not. Implanting boron into the substrate makes the semiconductor material less likely to invert thereby increasing the trip voltage to, for instance, 1 V.
During this V.sub.T adjust implant a material, usually boron, is implanted through the gate oxide into the substrate before the P1 and P2 layers are formed. This implant permeates all substrate areas covered by the thin gate oxide, which includes what will become the transistor channel areas, and increases the P-type doping concentration and therefore increases the threshold voltage.
A Flash E.sup.2 PROM cell has various problems which can occur during the erase of a charge on the floating gate, problems which result from the boron implant to adjust the threshold voltage. The problems increase as the level of boron in the substrate (specifically in the channel region of the transistor) is increased, and decrease as the level of boron decreases.
A first problem, impact ionization, occurs as the voltage potential across the source and the control gate increases. During an erase, the control gate is held at a low voltage, for instance 0 V, while a high voltage, for example 15 V, is applied to the source region. During impact ionization, the floating gate and source are "shorted" which causes an uncontrolled erasure of the floating gate, and therefore an overerase (i.e. depletion mode) of the floating gate can occur. While the mechanism is not known, it is believed that either the electrons tunnel through the thin gate oxide to the source, or that holes are transferred to the floating gate. The charges on the other floating gates on the device erase at a normal rate, and therefore an uneven erase occurs over the transistor array.
A second problem which can occur is junction breakdown, also referred to as avalanche breakdown. This occurs when the current from the source disperses into the grounded substrate. Normally, an electric field results from the 0 V on the control gate and the 15 V on the source, thereby allowing the charge stored on the floating gate to tunnel to the source. If the junction breakdown occurs at 14 V, for instance, the voltage on the source can never reach 15 V and the charge on the floating gate cannot be erased.
A PROM design which protects against the undesired phenomena of impact ionization and junction breakdown resulting from a V.sub.T adjust implant of boron or other positively charged majority carriers as listed above would be a desireable structure.